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`timescale 1us/1us
`ifndef EATER_REGISTER
`define EATER_REGISTER
module eater_register #(
parameter DATA_WIDTH = 8
) (
input wire clk_in,
// store data on rising clk?
input wire en_store_in,
// async - output data to bus
input wire en_output_in,
input wire [(DATA_WIDTH-1) : 0] data_in,
output wire [(DATA_WIDTH-1) : 0] bus_out,
output wire [(DATA_WIDTH-1) : 0] always_out
// inout [(DATA_WIDTH-1) : 0] data
);
reg [(DATA_WIDTH-1) : 0] r_datastore /* verilator public */;
always @(posedge clk_in) begin
if (en_store_in) begin
r_datastore <= data_in;
// r_datastore <= data;
end
end
assign bus_out = en_output_in ? r_datastore : 8'bz;
assign always_out = r_datastore;
// assign data = en_output_in ? r_datastore : 8'bz;
endmodule
`endif
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