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`timescale 1us/1us
`ifndef EATER_REGISTER
`define EATER_REGISTER
module eater_register #(
parameter DATA_WIDTH = 8
) (
input clk_i,
// store data on rising clk?
input en_store_i,
// async - output data to bus
input en_output_i,
input [(DATA_WIDTH-1) : 0] data_i,
output [(DATA_WIDTH-1) : 0] data_o
// inout [(DATA_WIDTH-1) : 0] data
);
reg [(DATA_WIDTH-1) : 0] r_datastore /* verilator public */;
always @(posedge clk_i) begin
if (en_store_i) begin
r_datastore <= data_i;
// r_datastore <= data;
end
end
assign data_o = en_output_i ? r_datastore : 8'bz;
// assign data = en_output_i ? r_datastore : 8'bz;
endmodule
`endif
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