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`timescale 1us/1us
module fizzbuzz_tb;
logic [7:0] number;
logic clk_i;
logic [7:0] num_out;
fizzbuzz uut (
.num_i(number),
.num_o(num_out),
.fizz_o(),
.buzz_o(),
.fizzbuzz_o()
);
string filename;
initial begin
`ifdef DUMP_FILE_NAME
filename=`DUMP_FILE_NAME;
`else
filename="fizzbuzz.lxt2";
`endif
$dumpfile(filename); $dumpvars();
clk_i = 0;
number = '0;
end
always #10 begin
clk_i = ~clk_i;
end
always @(negedge clk_i) begin
number <= number + 1;
// give iverilog some simulation time...
#1;
if (number == 3) assert(num_out == 0);
if (number == 5) assert(num_out == 0);
if (number == 15) assert(num_out == 0);
if (number == 255) $finish;
end
endmodule
|
