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`timescale 1us/1us
`include "clkdiv.v"
module led (
input clk, // clk input
input rst_i, // reset input
output reg [5:0] led_o // 6 LEDS pin
);
reg half_sec_clock;
clkdiv half_sec_divider(
.rst_i(rst_i),
.clk(clk),
.o_divclk(half_sec_clock)
);
always @(posedge half_sec_clock or negedge rst_i) begin
if (!rst_i)
led_o <= 6'b111111;
else
// else if (counter == 24'd1349_9999) // 0.5s delay
led_o[5:0] <= led_o[5:0] - 1;
// else
// led_o <= led_o;
end
endmodule
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