led.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

`include "clkdiv.v"

module led (
    input clk,              // clk input
    input rst_i,              // reset input
    output reg [5:0] led    // 6 LEDS pin
);

reg half_sec_clock;

clkdiv half_sec_divider(
  .rst_i(rst_i),
  .clk(clk),
  .o_divclk(half_sec_clock)
);

always @(posedge half_sec_clock or negedge rst_i) begin
    if (!rst_i)
        led <= 6'b111111;
    else
//    else if (counter == 24'd1349_9999)       // 0.5s delay
        led[5:0] <= led[5:0] - 1;
//    else
//        led <= led;
end


endmodule