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module led (
input clk, // clk input
input rst_i, // reset input
output reg [5:0] led // 6 LEDS pin
);
reg [23:0] counter;
always @(posedge clk or negedge rst_i) begin
if (!rst_i)
counter <= 24'd0;
else if (counter < 24'd1349_9999) // 0.5s delay
counter <= counter + 1'b1;
else
counter <= 24'd0;
end
always @(posedge clk or negedge rst_i) begin
if (!rst_i)
led <= 6'b111110;
else if (counter == 24'd1349_9999) // 0.5s delay
led[5:0] <= led[5:0] - 1;
else
led <= led;
end
endmodule
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