1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
|
// LLM generated, because I'm too lazy to do this manually
`timescale 1us/1ns
module my_mem_tb();
localparam DATA_WIDTH = 8;
localparam DATA_DEPTH = 16;
localparam ADDR_WIDTH = $clog2(DATA_DEPTH);
// DUT signals
logic clk;
logic write_en_i;
logic read_en_i;
logic [ADDR_WIDTH-1:0] r_read_addr;
logic [ADDR_WIDTH-1:0] r_write_addr;
logic [DATA_WIDTH-1:0] data_i;
logic [DATA_WIDTH-1:0] data_o;
// Instantiate DUT
my_mem #(
.DATA_WIDTH(DATA_WIDTH),
.DATA_DEPTH(DATA_DEPTH)
) dut (
.clk_i(clk),
.write_en_i(write_en_i),
.read_en_i(read_en_i),
.r_read_addr(r_read_addr),
.r_write_addr(r_write_addr),
.data_i(data_i),
.data_o(data_o)
);
string filename;
initial begin
`ifdef DUMP_FILE_NAME
filename=`DUMP_FILE_NAME;
`else
filename="my_mem.lxt2";
`endif
$dumpfile(filename); $dumpvars();
end
// Clock generator
always #10 clk = ~clk;
// Test sequence
initial begin
clk = 0;
write_en_i = 0;
read_en_i = 0;
r_read_addr = '0;
r_write_addr = '0;
data_i = '0;
repeat (3) @(posedge clk);
// -------------------------
// Write some values
// -------------------------
@(posedge clk);
#1
write_en_i = 1;
r_write_addr = 10;
data_i = 8'hA5;
@(posedge clk);
#1
r_write_addr = 11;
data_i = 8'h3C;
@(posedge clk);
#1
write_en_i = 0;
// -------------------------
// Read back values
// -------------------------
// asserts fail in iverilog if I use the posedge stuff,
// (but works in verilator).
// need an additional clock cycle delay.
@(posedge clk);
#1
read_en_i = 1;
r_read_addr = 10;
@(posedge clk);
#1
assert (data_o == 8'hA5)
else $error("ASSERTION FAILED: addr 10 expected 0xA5, got 0x%02h", data_o);
@(posedge clk);
#1
r_read_addr = 11;
@(posedge clk);
#1
assert (data_o == 8'h3C)
else $error("ASSERTION FAILED: addr 11 expected 0x3C, got 0x%02h", data_o);
@(posedge clk);
#1
read_en_i = 0;
repeat (3) @(posedge clk);
$finish;
end
endmodule
|
