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`timescale 1us/1us
`include "../my_mem.v"
`include "comb_mem.sv"
`include "instruction_decode.sv"
`include "counter.sv"
module computer (
input clk_i
);
wire nclk;
assign nclk = ~clk_i;
logic [15:0] PC_addr;
logic [15:0] PC_content;
my_mem #(
.DATA_WIDTH(16)
) ROM (
.clk_i(nclk),
.write_en_i(0),
.read_en_i(1),
.r_read_addr(PC_addr),
.r_write_addr(0),
.data_i(0),
.data_o(PC_content)
);
logic [15:0] out_A, out_D, out_pA;
logic in_store_A, in_store_D, in_store_pA;
logic [15:0] CPU_RES;
comb_mem #(
.DATA_WIDTH(16)
) RAM (
.cl(clk_i),
.A_o(out_A),
.D_o(out_D),
.pA_o(out_pA),
.a_i(in_store_A),
.d_i(in_store_D),
.pa_i(in_store_pA),
.X(CPU_RES)
);
logic cpu_jump;
instruction_decode CPU (
.instruction(PC_content),
.do_jump(cpu_jump),
.dst_a(in_store_A),
.dst_d(in_store_D),
.dst_pa(in_store_pA),
.A_i(out_A),
.D_i(out_D),
.pA_i(out_pA),
.RES(CPU_RES)
);
counter PC (
.cl(clk_i),
.count(PC_addr),
.X(out_A),
.st(cpu_jump)
);
endmodule
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