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// represents the final nandgame computer
`timescale 1us/1us
`include "../playground/my_mem.v"
`include "comb_mem.sv"
`include "instruction_decode.sv"
`include "counter.sv"
module computer (
input clk_in,
output halt
);
wire nclk_int;
assign nclk_int = ~clk_in;
logic [15:0] PC_addr_int /* verilator public */;
logic [15:0] PC_content_int /* verilator public */;
my_mem #(
.DATA_WIDTH(16),
.DATA_DEPTH(65536)
) ROM (
.clk_i(nclk_int),
.write_en_i(0),
.read_en_i(1),
.r_read_addr(PC_addr_int),
.r_write_addr(0),
.data_i(0),
.data_o(PC_content_int)
);
logic [15:0] reg_A_int /* verilator public */,
reg_D_int /* verilator public */,
reg_pA_int /* verilator public */;
logic store_to_A_int /* verilator public */,
store_to_D_int /* verilator public */,
store_to_pA_int /* verilator public */;
logic [15:0] result_int /* verilator public */;
comb_mem #(
.DATA_WIDTH(16)
) RAM (
.clk_in(clk_in),
.reg_A_out(reg_A_int),
.reg_D_out(reg_D_int),
.reg_pA_out(reg_pA_int),
.store_to_a_in(store_to_A_int),
.store_to_d_in(store_to_D_int),
.store_to_pa_in(store_to_pA_int),
.X_in(result_int)
);
logic cpu_do_jump_int /* verilator public */;
instruction_decode CPU (
.instruction_in(PC_content_int),
.do_jump_out(cpu_do_jump_int),
.dst_A_out(store_to_A_int),
.dst_D_out(store_to_D_int),
.dst_pA_out(store_to_pA_int),
.A_in(reg_A_int),
.D_in(reg_D_int),
.pA_in(reg_pA_int),
.result_out(result_int),
.invalid_ins(halt)
);
counter PC (
.clk_in(clk_in),
.counter_out(PC_addr_int),
.X_in(reg_A_int),
.st_store_X_in(cpu_do_jump_int)
);
`ifdef VERILATE
initial begin
$dumpfile("simpc.vvp"); $dumpvars();
end
`endif
endmodule
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