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// nandgame counter
`timescale 1us/1us
module counter #(
parameter DATA_WIDTH = 16
) (
// input / value to store in counter
input [(DATA_WIDTH-1):0] X_in,
// whether to store input (else increment)
input wire st_store_X_in,
// clock
input wire clk_in,
// counter value
output wire [(DATA_WIDTH-1):0] counter_out
);
/*
A counter component increments a 16-bit number for each clock cycle.
If st_store_X_in (store) is 1, then the input value X_in is used as the new counter value.
If st_store_X_in is 0, then the previous counter value is incremented by 1.
The counter output changes when clk_in (clock signal) changes to 0.
Input Effect
st_store_X_in clk_in
0 0 set next to output + 1
1 0 set next to X_in
output is the current output of the component. next becomes the current output when clk_in changes to 0.
*/
reg [(DATA_WIDTH-1):0] counter_int;
initial begin
counter_int = 0;
end
always @(negedge clk_in) begin
if (st_store_X_in)
counter_int <= X_in;
else
counter_int <= counter_int + 1;
end
assign counter_out = counter_int;
endmodule
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