blob: 87ecdd725dcc384be815416f03109d463c85b138 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
// nandgame counter
// counts on *falling* edge
`timescale 1us/1us
`ifndef NANDGAME_COUNTER
`define NANDGAME_COUNTER
module counter #(
parameter DATA_WIDTH = 16
) (
// input / value to store in counter
input wire [(DATA_WIDTH-1):0] X_in,
// whether to store input (else increment)
input wire st_store_X_in,
// clock
input wire clk_in,
// active high, whether to count
// st_store_X_in overrides this in any case.
input wire count_enable_in,
// counter value
output wire [(DATA_WIDTH-1):0] counter_out
);
/*
A counter component increments a 16-bit number for each clock cycle.
If st_store_X_in (store) is 1, then the input value X_in is used as the new counter value.
If st_store_X_in is 0, then the previous counter value is incremented by 1.
The counter output changes when clk_in (clock signal) changes to 0.
Input Effect
st_store_X_in clk_in
0 0 set next to output + 1
1 0 set next to X_in
output is the current output of the component. next becomes the current output when clk_in changes to 0.
*/
reg [(DATA_WIDTH-1):0] counter_int;
initial begin
counter_int = 0;
end
always @(negedge clk_in) begin
if (st_store_X_in)
counter_int <= X_in;
else if (count_enable_in)
counter_int <= counter_int + 1;
end
assign counter_out = counter_int;
endmodule
`endif
|
