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// nandgame counter
`timescale 1us/1us
module counter #(
parameter DATA_WIDTH = 16
) (
input [(DATA_WIDTH-1):0] X,
input wire st,
// probably opposed to nandgame,
// which "stores" on rising clock
// and "outputs" on falling clock,
// use "regular" stuff???
input wire cl,
output wire [(DATA_WIDTH-1):0] count
);
/*
A counter component increments a 16-bit number for each clock cycle.
If st (store) is 1, then the input value X is used as the new counter value.
If st is 0, then the previous counter value is incremented by 1.
The counter output changes when cl (clock signal) changes to 0.
Input Effect
st cl
0 0 set next to output + 1
1 0 set next to X
output is the current output of the component. next becomes the current output when cl changes to 0.
*/
reg [(DATA_WIDTH-1):0] r_ctr;
initial begin
r_ctr = 0;
end
always @(negedge cl) begin
if (st)
r_ctr <= X;
else
r_ctr <= r_ctr + 1;
end
assign count = r_ctr;
endmodule
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