1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
|
// HACK / nand2tetris ALU
`timescale 1us/1us
`include "nandgame_types.v"
`include "arith_unit.sv"
`include "logic_unit.sv"
`ifndef NANDGAME_ALU
`define NANDGAME_ALU
// See fig. 2.6 in book
module alu #(
parameter DATA_WIDTH = 16
) (
// "X" operand
input [(DATA_WIDTH-1):0] X_in,
// "Y" operand
input [(DATA_WIDTH-1):0] Y_in,
// zero X
input zx,
// negate X
input nx,
// zero Y
input zy,
// negate Y
input ny,
// "u" flag. 1=add, 0=and
input logic f_arith_nlogic_in,
// negate output
input logic neg_out,
// result of operation
output logic [(DATA_WIDTH-1):0] result_out,
// Result is zero
output logic zero_out,
// result is negative
output logic negate_out
);
logic [(DATA_WIDTH-1):0] int_op_x /* verilator public */;
logic [(DATA_WIDTH-1):0] int_op_y /* verilator public */;
// logic [(DATA_WIDTH-1):0] int_result_arith;
// logic [(DATA_WIDTH-1):0] int_result_logic;
// assign int_op_x = zx_in ? 0
// : (sw_in ? Y_in : X_in);
// assign int_op_y = sw_in ? X_in : Y_in;
// arith_unit au (
// .X_in(int_op_x),
// .Y_in(int_op_y),
// .result_out(int_result_arith),
// .arith_operation_in(ArithCode'(opcode_in))
// );
// logic_unit lu (
// .X_in(int_op_x),
// .Y_in(int_op_y),
// .result_out(int_result_logic),
// .logic_operation_in(LogicCode'(opcode_in))
// );
// assign result_out = u_arith_nlogic_in ? int_result_arith : int_result_logic;
endmodule
`endif
|
