par_to_ser.tb.v


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`timescale 1us/1ns

module par_to_ser_tb (
);

reg clk_i;
reg rst_i;
reg data_valid_i;
reg [7:0] dat_i;
wire dat_o;

par_to_ser uut(
  .clk_i(clk_i),
  .rst_i(rst_i),
  .data_valid_i(data_valid_i),
  .dat_i(dat_i),
  .dat_o(dat_o)
);

initial begin
  $dumpfile("par_to_ser.lxt2"); $dumpvars();
  clk_i <= 0;
  rst_i <= 1'b1;
  data_valid_i <= 1'b0;

  #1
  rst_i <= 1'b0;
  #1
  rst_i <= 1'b1;
end

always #10 clk_i = ~clk_i;

initial begin
  #37
  dat_i <= 8'b00110010;
  #13
  data_valid_i <= 1'b1;

  // clock data in
  #20

  // let module do its work
  data_valid_i <= 1'b0;

  #500
  $finish();
end

endmodule