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// parallel to serial converter
module par_to_ser (
input rst_i,
input clk_i,
input data_valid_i,
input [7:0] dat_i,
output reg dat_o
);
reg sending = 1'b0;
reg [7:0] send_data = 8'hff;
// Learning:
// Ugh, this is fucking stupid.
// if I send out directly at the rising clock edge,
// the output, when directly used again with the same clock,
// will violate setup and hold times???
//
always @(posedge clk_i or negedge rst_i) begin
if (!rst_i) begin
dat_o <= 1'b1;
sending <= 1'b0;
send_data <= 8'hff;
end else if (data_valid_i && !sending) begin
sending <= 1;
dat_o <= dat_i[0];
send_data <= {1'b1, dat_i[7:1]};
end else if (!data_valid_i) begin
sending <= 1'b0;
dat_o <= 1'b1;
end else if (sending) begin
dat_o <= send_data[0];
// arbitrary decision: register is filled with a 1
send_data <= {1'b1, send_data[7:1]};
end
end
endmodule
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