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`timescale 1us/1us
module fizzbuzz (
input wire [7:0] num_i,
output wire [7:0] num_o,
output wire fizz_o,
output wire buzz_o,
output wire fizzbuzz_o
);
wire is_fizz, is_buzz;
assign is_fizz = num_i % 3 == 0;
assign is_buzz = num_i % 5 == 0;
assign fizz_o = is_fizz && !is_buzz;
assign buzz_o = !is_fizz && is_buzz;
assign fizzbuzz_o = is_fizz && is_buzz;
assign num_o = (is_fizz || is_buzz) ? 0 : num_i;
endmodule
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