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`timescale 1us/1us
`ifndef UVOK_MEMORY
`define UVOK_MEMORY
module my_mem #(
parameter DATA_WIDTH = 8,
parameter DATA_DEPTH = 1024
) (
input clk_i,
input write_en_i,
input read_en_i,
input [$clog2(DATA_DEPTH)-1:0] r_read_addr,
input [$clog2(DATA_DEPTH)-1:0] r_write_addr,
input [(DATA_WIDTH-1) : 0] data_i,
output reg [(DATA_WIDTH-1) : 0] data_o,
output [(DATA_WIDTH-1) : 0] async_data_o
);
reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0] /* verilator public */;
`ifdef VERILATE
initial begin
r_datastore[0] = 'h11;
r_datastore[1] = 'h22;
r_datastore[2] = 'h33;
r_datastore[3] = 'h44;
r_datastore[4] = 'h55;
r_datastore[5] = 'h66;
r_datastore[6] = 'h77;
r_datastore[7] = 'h88;
end
`endif
`ifdef DEBUG
// for debugging simulations, as iverilog
// does't show r_datastore
reg [(DATA_WIDTH-1) : 0] r_cur_r_val;
reg [(DATA_WIDTH-1) : 0] r_cur_w_val;
`endif
always @(posedge clk_i) begin
if (write_en_i) begin
r_datastore[r_write_addr] <= data_i;
`ifdef DEBUG
r_cur_w_val <= data_i;
`endif
end
if (read_en_i) begin
data_o <= r_datastore[r_read_addr];
`ifdef DEBUG
r_cur_r_val <= r_datastore[r_read_addr];
`endif
end
end
assign async_data_o = r_datastore[r_read_addr];
endmodule
`endif
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