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`timescale 1us/1ns module template_tb ( ); reg clk_i; reg rst_i; template uut( .clk_i(clk_i), .rst_i(rst_i) ); initial begin $dumpfile("template.lxt2"); $dumpvars(); clk_i <= 0; rst_i <= 1'b1; end always #10 clk_i = ~clk_i; initial begin #100 $finish(); end endmodule