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authoruvok cheetah2026-01-06 16:17:12 +0100
committeruvok cheetah2026-01-06 16:17:12 +0100
commit7e2dc391484a29796364a1da8c1c3fdb5160f9df (patch)
tree6f133b0144fd433b42ae73d0314db4c4d4ccc39d
parenta2081a4c3e1488f4c3bc9ac1b71ca114f5ae4c56 (diff)
-rw-r--r--_posts/2026-01-06-getting-started-with-verilog.md (renamed from _posts/2026-01-06-getting-started-with-my-fpga-board-and-verilog.md)2
1 files changed, 1 insertions, 1 deletions
diff --git a/_posts/2026-01-06-getting-started-with-my-fpga-board-and-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md
index da08908..8eaf5f4 100644
--- a/_posts/2026-01-06-getting-started-with-my-fpga-board-and-verilog.md
+++ b/_posts/2026-01-06-getting-started-with-verilog.md
@@ -1,6 +1,6 @@
---
layout: post
-title: Getting started with my FPGA board and Verilog
+title: Getting started with Verilog
date: 2026-01-06 15:52 +0100
categories: tech
lang: en