Rename verilog series include

3 files changed, 3 insertions, 3 deletions

diff --git a/_posts/2025-12-26-fpga-dev-board.md b/_posts/2025-12-26-fpga-dev-board.md
index 49380c4..7bb0280 100644
--- a/_posts/2025-12-26-fpga-dev-board.md
+++ b/_posts/2025-12-26-fpga-dev-board.md
@@ -7,7 +7,7 @@ date: 2025-12-26 16:31 +0100
 description: "Showing off my FPGA dev board."
 ---
 
-{% include verilog.md %}
+{% include series_verilog.md %}
 
 For quite some time now, I wanted to experiment with FPGAs. As it is,
 there's lack of time, energy and motivation. And, also for me, the
diff --git a/_posts/2026-01-06-getting-started-with-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md
index e3b3e14..33672b4 100644
--- a/_posts/2026-01-06-getting-started-with-verilog.md
+++ b/_posts/2026-01-06-getting-started-with-verilog.md
@@ -7,7 +7,7 @@ lang: en
 description: "First experiments with Verilog, mostly simuluated."
 ---
 
-{% include verilog.md %}
+{% include series_verilog.md %}
 
 After I got my [FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %}), I
 have several books in my virtual library (Humble Bundle etc.) and decided to
diff --git a/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md b/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
index 63d8951..539271e 100644
--- a/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
+++ b/_posts/2026-03-22-verilog-how-does-a-cpu-actually-work.md
@@ -7,7 +7,7 @@ date: 2026-03-22 16:55 +0100
 description: How to write a CPU in Verilog
 ---
 
-{% include verilog.md %}
+{% include series_verilog.md %}
 
 A.k.a. "What's a fetch-decode-execute" cycle?