Include TOC for Verilog seriesHEADmaster

2 files changed, 4 insertions, 0 deletions

diff --git a/_posts/2025-12-26-fpga-dev-board.md b/_posts/2025-12-26-fpga-dev-board.md
index 17c871e..49380c4 100644
--- a/_posts/2025-12-26-fpga-dev-board.md
+++ b/_posts/2025-12-26-fpga-dev-board.md
@@ -7,6 +7,8 @@ date: 2025-12-26 16:31 +0100
 description: "Showing off my FPGA dev board."
 ---
 
+{% include verilog.md %}
+
 For quite some time now, I wanted to experiment with FPGAs. As it is,
 there's lack of time, energy and motivation. And, also for me, the
 urge to "find the perfect solution", in this case, the perfect
diff --git a/_posts/2026-01-06-getting-started-with-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md
index 994699b..e3b3e14 100644
--- a/_posts/2026-01-06-getting-started-with-verilog.md
+++ b/_posts/2026-01-06-getting-started-with-verilog.md
@@ -7,6 +7,8 @@ lang: en
 description: "First experiments with Verilog, mostly simuluated."
 ---
 
+{% include verilog.md %}
+
 After I got my [FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %}), I
 have several books in my virtual library (Humble Bundle etc.) and decided to
 start with Verilog. The book contained a few exercises which I tried to