Include TOC for Verilog seriesHEADmaster

1 files changed, 7 insertions, 0 deletions

diff --git a/assets/main.scss b/assets/main.scss
index b5f2fa5..6a6e664 100644
--- a/assets/main.scss
+++ b/assets/main.scss
@@ -88,6 +88,13 @@ hr.postsep {
   display: none;
 }
 
+hr.spaced.bottom {
+  margin-bottom: 1em;
+}
+hr.spaced.top {
+  margin-bottom: 0.5em;
+}
+
 /*
 PUSH CSS VERSION!
 */