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@@ -5,9 +5,10 @@ lang: en
categories: tech
date: 2026-03-22 16:55 +0100
description: How to write a CPU in Verilog
+series: Verilog
---
-{% include series_verilog.md %}
+{% include series.md %}
A.k.a. "What's a fetch-decode-execute" cycle?