Add link to (S)Verilog datatype

1 files changed, 4 insertions, 0 deletions

diff --git a/README.txt b/README.txt
index f040223..5ff79e7 100644
--- a/README.txt
+++ b/README.txt
@@ -36,3 +36,7 @@ Questions:
     It "somehow just works".
     Or rather, stuff is delayed by one clock cycle, e.g.
     when chaining flip-flops together.
+
+# Random links
+
+https://chipmunklogic.com/digital-logic-design/logic-vs-wire-in-system-verilog-some-misconceptions/