Questions

1 files changed, 5 insertions, 0 deletions

diff --git a/README.txt b/README.txt
index 7d8c29e..014cea5 100644
--- a/README.txt
+++ b/README.txt
@@ -4,3 +4,8 @@ Learnings:
   => wire's can't be assigned in always blocks, yosys complains
 - regs must not lead to wires? (unsure where I read that)
 - Clock on the tang9k is 27 MHz
+
+Questions:
+
+- Why do so many examples use always @(posedge clk or nededge rst).
+  i.e., why is the clk always included?