(System)Verilog: Be explicit about wire/logic

1 files changed, 3 insertions, 3 deletions

diff --git a/nandgame/arith_unit.sv b/nandgame/arith_unit.sv
index 53ea17e..75736ab 100644
--- a/nandgame/arith_unit.sv
+++ b/nandgame/arith_unit.sv
@@ -11,11 +11,11 @@ module  arith_unit #(
   parameter DATA_WIDTH = 16
 ) (
   // first operand
-  input [(DATA_WIDTH-1):0] X_in,
+  input wire [(DATA_WIDTH-1):0] X_in,
   // second operand
-  input [(DATA_WIDTH-1):0] Y_in,
+  input wire [(DATA_WIDTH-1):0] Y_in,
   // opcode, see ArithCode
-  input ArithCode arith_operation_in,
+  input wire ArithCode arith_operation_in,
 
   // result of operation
   output logic [(DATA_WIDTH-1):0] result_out