(System)Verilog: Be explicit about wire/logic

1 files changed, 2 insertions, 2 deletions

diff --git a/nandgame/computer.sv b/nandgame/computer.sv
index 5c2127f..3286bfe 100644
--- a/nandgame/computer.sv
+++ b/nandgame/computer.sv
@@ -8,8 +8,8 @@
 `include "counter.sv"
 
 module computer (
-  input clk_in,
-  output halt
+  input wire clk_in,
+  output wire halt
 );
 
 wire nclk_int;