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| author | uvok | 2026-01-16 18:22:10 +0100 |
|---|---|---|
| committer | uvok | 2026-01-16 18:22:36 +0100 |
| commit | 47c26f27b8be4c6c22ed81f701f1b25072bb3341 (patch) | |
| tree | b4baf08315beb28bcb00c7075413e2462db185af /nandgame/cond_check.sv | |
| parent | dd222c33ae00eb9312cb34610efd886dc565c159 (diff) | |
(System)Verilog: Be explicit about wire/logic
Diffstat (limited to 'nandgame/cond_check.sv')
| -rw-r--r-- | nandgame/cond_check.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/nandgame/cond_check.sv b/nandgame/cond_check.sv index 3961313..6aa8289 100644 --- a/nandgame/cond_check.sv +++ b/nandgame/cond_check.sv @@ -9,7 +9,7 @@ module cond_check #( parameter DATA_WIDTH = 16 ) ( // operand - input [(DATA_WIDTH-1):0] X_in, + input wire [(DATA_WIDTH-1):0] X_in, // check whether operand < 0 input wire check_ltz_in, // check whether operand == 0 |