diff options
| author | uvok | 2026-01-16 18:22:10 +0100 |
|---|---|---|
| committer | uvok | 2026-01-16 18:22:36 +0100 |
| commit | 47c26f27b8be4c6c22ed81f701f1b25072bb3341 (patch) | |
| tree | b4baf08315beb28bcb00c7075413e2462db185af /nandgame/counter.sv | |
| parent | dd222c33ae00eb9312cb34610efd886dc565c159 (diff) | |
(System)Verilog: Be explicit about wire/logic
Diffstat (limited to 'nandgame/counter.sv')
| -rw-r--r-- | nandgame/counter.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/nandgame/counter.sv b/nandgame/counter.sv index 90afa9b..2089194 100644 --- a/nandgame/counter.sv +++ b/nandgame/counter.sv @@ -9,7 +9,7 @@ module counter #( parameter DATA_WIDTH = 16 ) ( // input / value to store in counter - input [(DATA_WIDTH-1):0] X_in, + input wire [(DATA_WIDTH-1):0] X_in, // whether to store input (else increment) input wire st_store_X_in, // clock |