(System)Verilog: Be explicit about wire/logic

1 files changed, 2 insertions, 2 deletions

diff --git a/playground/clkdiv.v b/playground/clkdiv.v
index b6f1419..442ff35 100644
--- a/playground/clkdiv.v
+++ b/playground/clkdiv.v
@@ -1,8 +1,8 @@
 `timescale 1us/1us
 
 module clkdiv (
-    input rst_i,
-    input clk,              // clk input
+    input wire rst_i,
+    input wire clk,              // clk input
     output reg o_divclk     // divided output (must be a reg, b/c it needs to keep state)
 );