(System)Verilog: Be explicit about wire/logic

1 files changed, 3 insertions, 3 deletions

diff --git a/playground/debounce.v b/playground/debounce.v
index 33dc22e..4c68e2e 100644
--- a/playground/debounce.v
+++ b/playground/debounce.v
@@ -1,9 +1,9 @@
 `timescale 1us/1us
 
 module debounce (
-  input rst_i,
-  input clk_i,
-  input signal_i,
+  input wire rst_i,
+  input wire clk_i,
+  input wire signal_i,
   output reg signal_o
 );