(System)Verilog: Be explicit about wire/logic

1 files changed, 5 insertions, 5 deletions

diff --git a/playground/fizzbuzz.v b/playground/fizzbuzz.v
index 0e34c58..d251198 100644
--- a/playground/fizzbuzz.v
+++ b/playground/fizzbuzz.v
@@ -1,11 +1,11 @@
 `timescale 1us/1us
 
 module fizzbuzz (
-  input [7:0] num_i,
-  output [7:0] num_o,
-  output fizz_o,
-  output buzz_o,
-  output fizzbuzz_o
+  input wire [7:0] num_i,
+  output wire [7:0] num_o,
+  output wire fizz_o,
+  output wire buzz_o,
+  output wire fizzbuzz_o
 );
 
 wire is_fizz, is_buzz;