(System)Verilog: Be explicit about wire/logic

1 files changed, 2 insertions, 2 deletions

diff --git a/playground/led.v b/playground/led.v
index e4f4281..bf402d2 100644
--- a/playground/led.v
+++ b/playground/led.v
@@ -3,8 +3,8 @@
 `include "clkdiv.v"
 
 module led (
-    input clk,              // clk input
-    input rst_i,              // reset input
+    input wire clk,              // clk input
+    input wire rst_i,              // reset input
     output reg [5:0] led_o    // 6 LEDS pin
 );