(System)Verilog: Be explicit about wire/logic

1 files changed, 4 insertions, 4 deletions

diff --git a/playground/led_toggle.v b/playground/led_toggle.v
index 3c54ee4..f26d3be 100644
--- a/playground/led_toggle.v
+++ b/playground/led_toggle.v
@@ -7,10 +7,10 @@
 `include "debounce.v"
 
 module led_toggle (
-  input rst_i,
-  input clk_i,
-  input key_i,
-  output [5:0] led
+  input wire rst_i,
+  input wire clk_i,
+  input wire key_i,
+  output wire [5:0] led
 );
 parameter STABLE_PERIOD = 50;