(System)Verilog: Be explicit about wire/logic

1 files changed, 3 insertions, 3 deletions

diff --git a/playground/led_toggle_bouncy.v b/playground/led_toggle_bouncy.v
index b05b472..8e783f2 100644
--- a/playground/led_toggle_bouncy.v
+++ b/playground/led_toggle_bouncy.v
@@ -4,9 +4,9 @@
 // bouncy variant
 
 module led_toggle_bouncy (
-  input clk_i,
-  input key_i,
-  output [5:0] led
+  input wire clk_i,
+  input wire key_i,
+  output wire [5:0] led
 );
 
 reg r_LED_1 = 1'b1;