diff options
| author | uvok | 2026-01-16 18:22:10 +0100 |
|---|---|---|
| committer | uvok | 2026-01-16 18:22:36 +0100 |
| commit | 47c26f27b8be4c6c22ed81f701f1b25072bb3341 (patch) | |
| tree | b4baf08315beb28bcb00c7075413e2462db185af /playground/template.v | |
| parent | dd222c33ae00eb9312cb34610efd886dc565c159 (diff) | |
(System)Verilog: Be explicit about wire/logic
Diffstat (limited to 'playground/template.v')
| -rw-r--r-- | playground/template.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/playground/template.v b/playground/template.v index e6f5280..2cbe671 100644 --- a/playground/template.v +++ b/playground/template.v @@ -1,8 +1,8 @@ `timescale 1us/1us module template ( - input rst_i, - input clk_i + input wire rst_i, + input wire clk_i ); always @(posedge clk_i or negedge rst_i) begin |