tst_delay: Fix testbench name

1 files changed, 1 insertions, 1 deletions

diff --git a/tst_delay.tb.v b/tst_delay.tb.v
index 835c93a..41a133a 100644
--- a/tst_delay.tb.v
+++ b/tst_delay.tb.v
@@ -1,7 +1,7 @@
 // try to figure out how iverilog samples edges
 `timescale 1us/1us
 
-module template_tb (
+module tst_delay_tb (
 );
 
 reg clk_i;