fpga-exper - FPGA experiments

Age	Commit message (Expand)	Author
11 hours	Add third assembler example	uvok
11 hours	Add second example	uvok
13 hours	Reorganize cpp files	uvok
27 hours	dias: Only return halt for simplified	uvok
37 hours	example: Make sure state is shown	uvok
2 days	Add assembler exampel	uvok
2 days	bit 14 unset (w/ 15 set) = illegal ins	uvok
2 days	Add LLM assembler	uvok
3 days	disas, c: Fix compilation, missing header	uvok
4 days	Add cmp instruction	uvok
4 days	disas: endianness	uvok
4 days	cb: specify endianness via arg	uvok
4 days	fix endianness of binary creator	uvok
4 days	add LLM-gened disas	uvok
4 days	py: Add single-instruction disas	uvok
4 days	disas: Fix for ye olde pyhton	uvok
5 days	Documentation	uvok
5 days	disas: Fix fixups	uvok
6 days	disas: Canonocalize AND dest, #0... to mov	uvok
6 days	Canonicalize ops	uvok
6 days	Nicer disas output	uvok
6 days	Improve assembler syntax	uvok
7 days	docu	uvok
7 days	createbin: avoid reserved bits	uvok
7 days	Add disas tests	uvok
7 days	finish disassembler	uvok
7 days	finish disasseembler	uvok
7 days	disas: move arg check in main	uvok
7 days	black format	uvok
7 days	disas: lowercase ops, arg decode	uvok
7 days	decode op and jumps	uvok
7 days	Start by bin creator and disassembler	uvok