fpga-exper - FPGA experiments

Age	Commit message (Expand)	Author
11 days	Use custom classes in parser, rearrange	uvok
11 days	py: Reformat files with black	uvok
11 days	lex: Don't warn about newline	uvok
11 days	Add shebangs, exec flag	uvok
11 days	Add previous parser experiments	uvok
11 days	automatic newline add	uvok
11 days	Include NL in lexer/parser	uvok
11 days	Add first version of assembler	uvok
12 days	Add third assembler example	uvok
12 days	Add second example	uvok
12 days	Reorganize cpp files	uvok
13 days	dias: Only return halt for simplified	uvok
13 days	example: Make sure state is shown	uvok
2026-01-09	Add assembler exampel	uvok
2026-01-09	bit 14 unset (w/ 15 set) = illegal ins	uvok
2026-01-09	Add LLM assembler	uvok
2026-01-08	disas, c: Fix compilation, missing header	uvok
2026-01-07	Add cmp instruction	uvok
2026-01-07	disas: endianness	uvok
2026-01-07	cb: specify endianness via arg	uvok
2026-01-07	fix endianness of binary creator	uvok
2026-01-07	add LLM-gened disas	uvok
2026-01-07	py: Add single-instruction disas	uvok
2026-01-07	disas: Fix for ye olde pyhton	uvok
2026-01-06	Documentation	uvok
2026-01-06	disas: Fix fixups	uvok
2026-01-05	disas: Canonocalize AND dest, #0... to mov	uvok
2026-01-05	Canonicalize ops	uvok
2026-01-05	Nicer disas output	uvok
2026-01-05	Improve assembler syntax	uvok
2026-01-04	docu	uvok
2026-01-04	createbin: avoid reserved bits	uvok
2026-01-04	Add disas tests	uvok
2026-01-04	finish disassembler	uvok
2026-01-04	finish disasseembler	uvok
2026-01-04	disas: move arg check in main	uvok
2026-01-04	black format	uvok
2026-01-04	disas: lowercase ops, arg decode	uvok
2026-01-04	decode op and jumps	uvok
2026-01-04	Start by bin creator and disassembler	uvok