| Age | Commit message (Expand) | Author |
|---|---|---|
| 3 days | bit 14 unset (w/ 15 set) = illegal ins | uvok |
| 3 days | Add LLM assembler | uvok |
| 3 days | disas, c: Fix compilation, missing header | uvok |
| 4 days | Add cmp instruction | uvok |
| 4 days | disas: endianness | uvok |
| 4 days | cb: specify endianness via arg | uvok |
| 5 days | fix endianness of binary creator | uvok |
| 5 days | add LLM-gened disas | uvok |
| 5 days | py: Add single-instruction disas | uvok |
| 5 days | disas: Fix for ye olde pyhton | uvok |
| 5 days | Documentation | uvok |
| 6 days | disas: Fix fixups | uvok |
| 7 days | disas: Canonocalize AND dest, #0... to mov | uvok |
| 7 days | Canonicalize ops | uvok |
| 7 days | Nicer disas output | uvok |
| 7 days | Improve assembler syntax | uvok |
| 8 days | docu | uvok |
| 8 days | createbin: avoid reserved bits | uvok |
| 8 days | Add disas tests | uvok |
| 8 days | finish disassembler | uvok |
| 8 days | finish disasseembler | uvok |
| 8 days | disas: move arg check in main | uvok |
| 8 days | black format | uvok |
| 8 days | disas: lowercase ops, arg decode | uvok |
| 8 days | decode op and jumps | uvok |
| 8 days | Start by bin creator and disassembler | uvok |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |