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|
4 LSB
+<--------> PC
|
|
4 LSB |
MAR <-------------+<--------> A
| | |
| 4 LSB | |
| | |
v | v
RAM <------------>|<-------- ALU
| ^
| |
| |
| |
<-------------+ |
IR ------------->|<--------> B
| 4 LSB |
| |
| |
| 4 MSB +---------> OUT
| |
v |
ins v
decoder DISPLAY
---
instruction set
NOP ____________ 0b_0000_xxxx No-op
LDA <memaddress> 0b_0001_<memaddress> Load memory > A
ADD <memaddress> 0b_0010_<memaddress> "Add memory": mem>B, A + B -> A
SUB <memaddress> 0b_0011_<memaddress> "Sub memory": mem>B, A - B-> A
STA <memaddress> 0b_0100_<memaddress> Store A -> memory
LDI <value> 0b_0101_<value> Store <value> -> A
JMP <address> 0b_0110_<address> <address> -> PC
OUT ____________ 0b_1110_xxxx Output A -> OUT
HLT ____________ 0b_1111_xxxx Sets halt flag
---
operation
1. Load instruction @ PC into INS,
Increment PC.
a) PC out -> MAR
(PC_to_bus) + (bus_to_MAR) + (clk)
b) MEM -> INS
(RAM_to_bus) + (bus_to_INS) + (clk)
c) PC++
(PC_count_en) + (clk)
NOTE:
Yes, I know Ben Eaters computer combines b and c.
See eater_types for details.
Actually, it occurred to me you can combine b and c,
if you like BE PC, run the decoder on the falling clock edge.
2. Decode and execute instruction.
2.I LDA: Load memory into A
a) INS_lsb -> MAR
(INS_to_bus) + (bus_to_MAR) + (clk)
b) MEM -> A
(RAM_to_bus) + (bus_to_A) + (clk)
2.II ADD: Load mem in B,
ALU "auto" adds,
put back in A
a) INS_lsb -> MAR
(INS_to_bus) + (bus_to_MAR) + (clk)
b) MEM -> B
(RAM_to_bus) + (bus_to_B) + (clk)
c) ALU -> A
(ALU_to_bus) + (bus_to_A) + (clk)
2.III OUT: Put A in OUT
a) A -> OUT
(A_to_bus) + (bus_to_OUT) + (clk)
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