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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: main() simulation loop, created with --main
#include "Vcomputer.h"
#include "Vcomputer___024root.h"
#include "Vcomputer_alu.h"
#include "Vcomputer_comb_mem.h"
#include "Vcomputer_computer.h"
#include "Vcomputer_instruction_decode.h"
#include "Vcomputer_my_mem__D10_DB10000.h"
#include "verilated.h"
#include <cinttypes>
#include <cstdint>
#include <cstdio>
#include <sched.h>
#define TICKS_PER_INS 2
#define NCUR 1
#include "../assembler/disas.h"
#define NCUR_X 5
#if NCUR
#include <ncurses.h>
#define NCUR_DELAY_MS 100
#define PRINT_ME(y, x, ...) \
{ \
mvprintw(y, x, __VA_ARGS__); \
}
#define PRINT_NEXT() \
{ \
refresh(); \
napms(NCUR_DELAY_MS); \
}
#else
#define PRINT_ME(y, x, ...) \
{ \
printf("%*c", x, ' '); \
printf(__VA_ARGS__); \
printf("\n"); \
}
#define PRINT_NEXT() \
{ \
puts("-----"); \
}
#endif
//======================
enum class StepPosition_t { BEFORE_EVAL, AFTER_EVAL };
void draw_ui(const std::unique_ptr<Vcomputer> &topp, uint64_t &i,
StepPosition_t sp) {
uint16_t opcode = topp->computer->PC_content_int;
PRINT_ME(1, 1, "Step: %10d \b%c", i,
sp == StepPosition_t::BEFORE_EVAL ? 'A' : 'B');
PRINT_ME(3, NCUR_X, "CLK1: %4d\tPC: @0x%04X\tINS: 0x%04X\tHLT: %d",
topp->clk_in,
// wrong
// topp->computer->clk_in,
topp->computer->PC_addr_int, opcode, topp->halt);
auto insline = print_decoded(opcode, true);
PRINT_ME(5, NCUR_X, "%-80s", insline.c_str());
PRINT_ME(7, NCUR_X, "A: 0x%04X\tD: 0x%04X\tM: 0x%04X\tRES: 0x%04X",
topp->computer->reg_A_int, topp->computer->reg_D_int,
topp->computer->reg_pA_int, topp->computer->result_int);
PRINT_ME(
8, NCUR_X, "%c%8d\t%c%8d\t%c%8d\t%11d",
topp->computer->store_to_A_int ? '*' : ' ', topp->computer->reg_A_int,
topp->computer->store_to_D_int ? '*' : ' ', topp->computer->reg_D_int,
topp->computer->store_to_pA_int ? '*' : ' ', topp->computer->reg_pA_int,
topp->computer->result_int);
#define MEMORY_CONTEXT 3
const int ram1_pos_offset = 35 + 1;
const int ram2_pos_offset = ram1_pos_offset + 14 + 1;
PRINT_ME(10, NCUR_X, "%-35s", "--- ROM ---");
PRINT_ME(10, NCUR_X + ram1_pos_offset, "%-35s", "--- RAM1 ---");
PRINT_ME(10, NCUR_X + ram2_pos_offset, "%-35s", "-- RAM2 --");
for (int i = -MEMORY_CONTEXT; i <= MEMORY_CONTEXT; i++) {
const int ypos_base = 10 + 1 + MEMORY_CONTEXT;
const char *prefix = i == 0 ? "> " : " ";
int32_t current_ROM_address = topp->computer->PC_addr_int + i;
int32_t current_RAM_address = topp->computer->reg_A_int + i;
if (current_ROM_address < 0) {
PRINT_ME(
ypos_base + i, NCUR_X, "%.35s",
"---------------------------------------------------------------");
} else {
const uint16_t p = current_ROM_address;
const uint16_t program_op_code = topp->computer->ROM->r_datastore[p];
auto disas_code = print_decoded(program_op_code, true);
PRINT_ME(ypos_base + i, NCUR_X, "%04X %s%04X %-30s",
current_ROM_address, prefix, program_op_code,
disas_code.c_str());
}
if (current_RAM_address < 0) {
PRINT_ME(
ypos_base + i, NCUR_X + ram1_pos_offset, "%.12s",
"---------------------------------------------------------------");
} else {
const uint16_t p = current_RAM_address;
const uint16_t mem_content =
topp->computer->RAM->nand_memory->r_datastore[p];
PRINT_ME(ypos_base + i, NCUR_X + ram1_pos_offset, "%04X %s%04X",
current_RAM_address, prefix, mem_content);
}
{
const uint16_t p = MEMORY_CONTEXT + i;
const uint16_t mem_content =
topp->computer->RAM->nand_memory->r_datastore[p];
PRINT_ME(ypos_base + i, NCUR_X + ram2_pos_offset, "%04X %04X%30c", p,
mem_content, ' ');
}
}
// PRINT_ME(7 + NCUR_OFFSET, NCUR_X, "ALU");
// PRINT_ME(8 + NCUR_OFFSET, NCUR_X, "X: %5d\tY: %5d",
// topp->computer->CPU->my_alu->int_op_x,
// topp->computer->CPU->my_alu->int_op_y);
PRINT_NEXT();
}
int main(int argc, char **argv, char **) {
// Setup context, defaults, and parse command line
Verilated::debug(0);
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::traceEverOn(true);
contextp->threads(1);
contextp->commandArgs(argc, argv);
// Construct the Verilated model, from Vtop.h generated from Verilating
const std::unique_ptr<Vcomputer> topp{new Vcomputer{contextp.get(), ""}};
if (argc != 2) {
fprintf(stderr, "Usage: %.20s [filename]\n\n", argv[0]);
exit(-1);
}
puts("Start simulation.");
// topp->computer->clk_in = 0;
topp->clk_in = 0;
FILE *f = fopen(argv[1], "rb");
if (!f) {
fprintf(stderr, "Program file %.20s not found.\n", argv[1]);
exit(-1);
}
fseek(f, 0, SEEK_END);
long fpos = ftell(f);
fseek(f, 0, SEEK_SET);
size_t bytes_read =
fread(topp->computer->ROM->r_datastore.m_storage, 2, fpos / 2, f);
if (bytes_read * 2 != fpos) {
fputs("Couldn't read program file completely.", stderr);
exit(-1);
}
#if NCUR
initscr();
curs_set(0);
#endif
while (VL_LIKELY(!contextp->gotFinish()) && contextp->time() < 500 &&
!topp->halt) {
auto i = contextp->time();
draw_ui(topp, i, StepPosition_t::BEFORE_EVAL);
// Evaluate model
if (i != 0 && (i % TICKS_PER_INS) == 0) {
topp->clk_in = !topp->clk_in;
}
topp->eval();
draw_ui(topp, i, StepPosition_t::AFTER_EVAL);
// Advance time
contextp->timeInc(1);
}
#if NCUR
refresh();
#endif
// PRINT_ME(9, 0, "%80c", ' ');
PRINT_ME(1, 30, "Simulation finished.");
const char *msg;
if (topp->halt) {
msg = "Halt encountered.";
} else if (!contextp->gotFinish()) {
msg = "Step count exceeded.";
} else {
msg = "Regular finish.";
}
PRINT_ME(2, 30, "%s", msg);
// PRINT_ME(12, 0, "%80c", ' ');
if (VL_LIKELY(!contextp->gotFinish())) {
VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
}
// for tracefile to properly show
for (int i = 0; i < 10; i++) {
contextp->timeInc(1);
topp->eval();
}
// Execute 'final' processes
topp->final();
// Print statistical summary report
// contextp->statsPrintSummary();
#if NCUR
getch();
endwin();
#endif
return 0;
}
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