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`timescale 1us/1us
module comb_mem_tb;
reg tst_clk;
logic tst_write_A, tst_write_D, tst_write_pA;
logic [15:0] tst_reg_A, tst_reg_D, tst_reg_pA;
logic [15:0] tst_X;
comb_mem uut (
.clk_in(tst_clk),
.store_to_a_in(tst_write_A),
.store_to_d_in(tst_write_D),
.store_to_pa_in(tst_write_pA),
.reg_A_out(tst_reg_A),
.reg_D_out(tst_reg_D),
.reg_pA_out(tst_reg_pA),
.X_in(tst_X)
);
string filename;
initial begin
`ifdef DUMP_FILE_NAME
filename=`DUMP_FILE_NAME;
`else
filename="comb_mem.lxt2";
`endif
$dumpfile(filename);
$dumpvars();
tst_clk = 0;
tst_write_A = 0; tst_write_D = 0; tst_write_pA = 0;
tst_X = 16'h55;
end
always #10 tst_clk = ~tst_clk;
initial begin
repeat(3) @(posedge tst_clk);
tst_X = 16'h02;
tst_write_A = 1;
repeat(3) @(posedge tst_clk);
tst_write_A = 0;
repeat(3) @(posedge tst_clk);
tst_X = 16'h55;
tst_write_A = 1;
repeat(3) @(posedge tst_clk);
assert (tst_reg_A == 16'h55)
else $error("Register A not written");
tst_write_A = 0;
tst_write_D = 1;
repeat(3) @(posedge tst_clk);
assert (tst_reg_D == 16'h55)
else $error("Register D not written");
tst_write_D = 0;
tst_write_pA = 1;
tst_X = 16'haa;
repeat(3) @(posedge tst_clk);
assert (tst_reg_pA == 16'haa)
else $error("Register pA not written");
$finish();
end
endmodule
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