Rename verilog series include

1 files changed, 12 insertions, 0 deletions

diff --git a/_includes/series_verilog.md b/_includes/series_verilog.md
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+
+---
+{: .spaced.top }
+
+## Verilog series
+
+0. [Presenting my FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %})
+1. [Getting Started with Verilog]({% post_url 2026-01-06-getting-started-with-verilog %})
+2. [How does a CPU actually work?]({% post_url 2026-03-22-verilog-how-does-a-cpu-actually-work %})
+
+---
+{: .spaced.bottom }