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authoruvok cheetah2026-06-14 19:08:38 +0200
committeruvok cheetah2026-06-14 19:08:38 +0200
commit522f98fc205d112897360fa90bbbef268aa66f48 (patch)
treee9c0dd479beef86e1e1d2d74cd64e27252bc91b6 /_posts/2025-12-26-fpga-dev-board.md
parente39a878420f355c8790fd62f60a0034181a4f2cd (diff)
Use auto-series
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diff --git a/_posts/2025-12-26-fpga-dev-board.md b/_posts/2025-12-26-fpga-dev-board.md
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--- a/_posts/2025-12-26-fpga-dev-board.md
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@@ -5,9 +5,10 @@ lang: en
categories: tech
date: 2025-12-26 16:31 +0100
description: "Showing off my FPGA dev board."
+series: Verilog
---
-{% include series_verilog.md %}
+{% include series.md %}
For quite some time now, I wanted to experiment with FPGAs. As it is,
there's lack of time, energy and motivation. And, also for me, the