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| author | uvok cheetah | 2026-06-14 19:08:38 +0200 |
|---|---|---|
| committer | uvok cheetah | 2026-06-14 19:08:38 +0200 |
| commit | 522f98fc205d112897360fa90bbbef268aa66f48 (patch) | |
| tree | e9c0dd479beef86e1e1d2d74cd64e27252bc91b6 /_posts/2026-01-06-getting-started-with-verilog.md | |
| parent | e39a878420f355c8790fd62f60a0034181a4f2cd (diff) | |
Use auto-series
Diffstat (limited to '_posts/2026-01-06-getting-started-with-verilog.md')
| -rw-r--r-- | _posts/2026-01-06-getting-started-with-verilog.md | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/_posts/2026-01-06-getting-started-with-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md index 33672b4..c0044c0 100644 --- a/_posts/2026-01-06-getting-started-with-verilog.md +++ b/_posts/2026-01-06-getting-started-with-verilog.md @@ -5,9 +5,10 @@ date: 2026-01-06 15:52 +0100 categories: tech lang: en description: "First experiments with Verilog, mostly simuluated." +series: Verilog --- -{% include series_verilog.md %} +{% include series.md %} After I got my [FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %}), I have several books in my virtual library (Humble Bundle etc.) and decided to |