Include TOC for Verilog seriesHEADmaster

1 files changed, 12 insertions, 0 deletions

diff --git a/_includes/verilog.md b/_includes/verilog.md
new file mode 100644
index 0000000..d89bbb0
--- /dev/null
+++ b/_includes/verilog.md
@@ -0,0 +1,12 @@
+
+---
+{: .spaced.top }
+
+## Verilog series
+
+0. [Presenting my FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %})
+1. [Getting Started with Verilog]({% post_url 2026-01-06-getting-started-with-verilog %})
+2. TODO
+
+---
+{: .spaced.bottom }