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| author | uvok cheetah | 2026-06-14 18:40:15 +0200 |
|---|---|---|
| committer | uvok cheetah | 2026-06-14 18:40:15 +0200 |
| commit | a40fbb874e226bf5368c8e5435fc322aa5d41a70 (patch) | |
| tree | 9c23cbc8eba6c81a9617d19ce6d71ff67712d16e /_posts/2025-12-26-fpga-dev-board.md | |
| parent | b3fae5622be937bf35a13325737beee1e3aaf923 (diff) | |
Rename verilog series include
Diffstat (limited to '_posts/2025-12-26-fpga-dev-board.md')
| -rw-r--r-- | _posts/2025-12-26-fpga-dev-board.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/_posts/2025-12-26-fpga-dev-board.md b/_posts/2025-12-26-fpga-dev-board.md index 49380c4..7bb0280 100644 --- a/_posts/2025-12-26-fpga-dev-board.md +++ b/_posts/2025-12-26-fpga-dev-board.md @@ -7,7 +7,7 @@ date: 2025-12-26 16:31 +0100 description: "Showing off my FPGA dev board." --- -{% include verilog.md %} +{% include series_verilog.md %} For quite some time now, I wanted to experiment with FPGAs. As it is, there's lack of time, energy and motivation. And, also for me, the |