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| author | uvok cheetah | 2026-03-15 13:52:55 +0100 |
|---|---|---|
| committer | uvok cheetah | 2026-03-15 13:52:55 +0100 |
| commit | f704e93efac8193447543e518068c3d0ad1c3689 (patch) | |
| tree | a8d97a1d011b54ecd014799391583f8b71b9f6e4 /_posts/2025-12-26-fpga-dev-board.md | |
| parent | b8ca4f6d585a23ef1c96ad8781bff533f30d4cc7 (diff) | |
Diffstat (limited to '_posts/2025-12-26-fpga-dev-board.md')
| -rw-r--r-- | _posts/2025-12-26-fpga-dev-board.md | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/_posts/2025-12-26-fpga-dev-board.md b/_posts/2025-12-26-fpga-dev-board.md index 17c871e..49380c4 100644 --- a/_posts/2025-12-26-fpga-dev-board.md +++ b/_posts/2025-12-26-fpga-dev-board.md @@ -7,6 +7,8 @@ date: 2025-12-26 16:31 +0100 description: "Showing off my FPGA dev board." --- +{% include verilog.md %} + For quite some time now, I wanted to experiment with FPGAs. As it is, there's lack of time, energy and motivation. And, also for me, the urge to "find the perfect solution", in this case, the perfect |