Rename verilog series include

1 files changed, 1 insertions, 1 deletions

diff --git a/_posts/2026-01-06-getting-started-with-verilog.md b/_posts/2026-01-06-getting-started-with-verilog.md
index e3b3e14..33672b4 100644
--- a/_posts/2026-01-06-getting-started-with-verilog.md
+++ b/_posts/2026-01-06-getting-started-with-verilog.md
@@ -7,7 +7,7 @@ lang: en
 description: "First experiments with Verilog, mostly simuluated."
 ---
 
-{% include verilog.md %}
+{% include series_verilog.md %}
 
 After I got my [FPGA dev board]({% post_url 2025-12-26-fpga-dev-board %}), I
 have several books in my virtual library (Humble Bundle etc.) and decided to